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general description the MAX7317 serial-interfaced peripheral provides microprocessors with 10 i/o ports rated to 7v. each port can be individually configured as either an open- drain output, or an overvoltage-protected schmitt input. the MAX7317 supports hot insertion. all port pins remain high impedance in power-down (v+ = 0v) with up to 8v asserted on them. the MAX7317 is available in 16-pin thin qfn and qsop packages and operates in the -40 c to +125 c range. for a similar part with constant-current outputs and 8-bit pwm controls, refer to the max6966/max6967 data sheet. applications portable equipment cellular phones white goods industrial controllers automotive system monitoring features ? high-speed, 26mhz spi-/qspi-/microwire- compatible serial interface ? 2.25v to 3.6v operation ? i/o port inputs are overvoltage protected to 7v ? i/o port outputs are 7v-rated open drain ? i/o ports support hot insertion ? 0.7? (typ), 1.9? (max) standby current ? tiny 3mm x 3mm, 0.8mm high thin qfn package ? -40? to +125? temperature range MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection ________________________________________________________________ maxim integrated products 1 12 11 10 9 p9 p8 p7 5 6 7 8 p4 gnd p6 16 15 14 13 cs sclk v+ 1234 p0 p1 p2 p3 din p5 dout thin qfn top view MAX7317ate pin configurations ordering information c din p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 dout sclk gnd mosi miso sclk cs cs i/o ports MAX7317 +3.3v typical application circuit 19-3380; rev 1; 1/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package top mark pkg code MAX7317ate -40 c to +125 c 16 thin qfn 3mm x 3mm x 0.8mm ach t1633-4 MAX7317aee -40 c to +125 c 16 qsop pin configurations continued at end of data sheet. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp.
MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics ( typical operating circuit , v+ = 2.25v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage (with respect to gnd) v+ .............................................................................-0.3v to +4v sclk, din, cs, dout .................................-0.3v to (v+ + 0.3v) p_ .............................................................................-0.3v to +8v dc current into p_ .............................................................24ma dc current into dout ........................................................10ma total gnd current ............................................................200ma continuous power dissipation (t a = +70?) 16-pin thin qfn (derate 14.7mw/? above +70?) .........................1176mw 16-pin qsop (derate 8.3mw/? above +70?)...........667mw operating temperature range (t min to t max ) ..............................................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units operating supply voltage v+ 2.25 3.60 v output load external supply voltage p0?9 v ext 7v t a = +25? 0.70 1.5 t a = t min to +85? 1.7 standby current (interface idle) i stby all digital inputs at v+ or gnd t a = t min to t max 1.9 ? t a = +25? 385 620 t a = t min to +85? 680 supply current i + f sclk = 26mhz; other digital inputs at v+ or gnd; dout unloaded t a = t min to t max 730 ? input high voltage (p0?9, din, sclk, cs ) v ih p0?9 output register set to 0x01 0.7 x v+ v input low voltage (p0?9, din, sclk, cs ) v il p0?9 output register set to 0x01 0.3 x v+ v input leakage current (p0?9, din, sclk, cs ) i ih , i il -0.2 +0.2 a input capacitance (p0?9, din, sclk, cs (note 2) 10 pf output low voltage (p0?9) v olp _ i sink = 0.5ma, output register set to 0x00 0.4 v output low short-circuit current (p0?9) v olpout = 5v 10.8 20 ma output high voltage (dout) v ohdout i source = -6ma v+ - 0.3v v output low voltage (dout) v oldout i sink = 6ma 0.3 v power-on reset voltage v por 2v
MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection _______________________________________________________________________________________ 3 note 1: all parameters are tested at t a = +25?. specifications over temperature are guaranteed by design. note 2: guaranteed by design. timing characteristics ( typical operating circuit , v+ = 2.25v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units sclk clock period t cp 38.4 ns sclk pulse-width high t ch 19 ns sclk pulse-width low t cl 19 ns cs fall to sclk rise setup t css 9.5 ns sclk rise to cs rise hold t csh 2.5 ns din setup time t ds 9.5 ns din hold time t dh 2.5 ns output data propagation delay t do 19 ns dout output rise and fall times t ft c load = 20pf (note 2) 10 ns minimum cs pulse high t csw 38.4 ns p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 i/o register 4-wire serial interface sclk din dout cs i/o ports MAX7317 MAX7317 block diagram
MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection 4 _______________________________________________________________________________________ typical operating characteristics (t a = +25?, unless otherwise noted.) 0 3 9 6 12 15 port sink current vs. port voltage MAX7317 toc01 port voltage (v) port sink current (ma) 04 268 t a = -40 c t a = +25 c t a = +85 c t a = +125 c 0.4 0.6 0.5 0.8 0.7 0.9 1.0 -40 -10 5 20 -25 35 50 65 80 95 110 125 standby current vs. temperature MAX7317 toc02 temperature ( c) standby current ( a) v+ = 3.6v v+ = 3.3v v+ = 2.7v v+ = 2.25v 0 0.1 0.3 0.2 0.4 0.5 -40 -10 5 20 -25 35 50 65 80 95 110 125 supply current (i+) vs. temperature MAX7317 toc03 temperature ( c) standby current (ma) v+ = 3.6v v+ = 3.3v v+ = 2.7v v+ = 2.25v pin qsop qfn name function 1 15 sclk serial-clock input. on sclk? rising edge, data shifts into the internal shift register. on sclk? falling edge, data is clocked out of dout. sclk is active only while cs is low. 216 cs chip-select input. serial data is loaded into the shift register while cs is low. the most recent 16 bits of data latch on cs ? rising edge. 3?, 9?3 1?, 7?1 p0?9 i/o ports. p0 to p9 can be configured as open-drain, current-sink outputs rated at 20ma maximum, or as cmos inputs, or as open-drain outputs. loads should be connected to a supply voltage no higher than 7v. 8 6 gnd ground 14 12 dout serial-data output. the data into din is valid at dout 15.5 clock cycles later. use this pin to daisy-chain several devices or allow data readback. output is push-pull. 15 13 din serial-data input. data from din loads into the internal 16-bit shift register on sclk? rising edge. 16 14 v+ positive supply voltage. bypass v+ to gnd with a 0.047? ceramic capacitor. pad exposed pad exposed pad on package underside. connect to gnd. pin description
detailed description the MAX7317 is a general-purpose input/output (gpio) peripheral that provides 10 i/o ports, p0 to p9, con- trolled through a high-speed spi-compatible serial interface. the 10 i/o ports can be used as inputs or open-drain outputs in any combination. ports withstand 7v independent of the MAX7317? supply voltage whether used as inputs or outputs. figure 1 shows the i/o port structure of the MAX7317. register structure the MAX7317 contains 10 internal registers, addressed as 0x00?x09, which control the peripheral (table 2). two further addresses, 0x0e and 0x0f, do not store data but return the port input status when read. four virtual addresses, 0x0a?x0d, allow more than one register to be written with the same data to simplify soft- ware. the ram register provides 1 byte of memory that can be used for any purpose. the no-op address, 0x20, causes no action when written or read, and is used as a dummy register when accessing one MAX7317 out of multiple cascaded devices. initial power-up on power-up, all control registers are reset (table 2). power-up status sets i/o ports p0 to p9 high imped- ance, and puts the device into shutdown mode. ram register the ram register provides a byte of memory that can be used for any purpose. gpio port direction configuration the 10 i/o ports p0 through p9 can be configured to any combination of inputs and outputs. ports withstand 7v independent of the MAX7317? supply voltage, whether used as inputs or outputs. configure a port as an input by setting its output register to 0x01, which sets the port output high impedance (table 4). input port registers reading an input port register returns the logic levels at the i/o port pins. the input port registers are read only. a write to an input port register is ignored. output registers the MAX7317 uses one 8-bit register to control each output port (table 4). each port can be configured as an input or open-drain output. write 0x00 to the output register to set the port as a logic-low output, or 0x01 to set the port as a logic-high output or logic input. the 10 registers, 0x00 through 0x09, control an i/o port each (table 4). four pseudo-register addresses, 0x0a through 0x0d, allow groups of outputs to be set to the same value with a single command by writing the same data to multiple output registers. serial interface the MAX7317 communicates through an spi-compati- ble 4-wire serial interface. the interface has three inputs: clock (sclk), chip select ( cs ), and data in (din), and one output, data out (dout). cs must be low to clock data into or out of the device, and din must be stable when sampled on the rising edge of sclk. dout is stable on the rising edge of sclk. sclk and din can be used to transmit data to other peripherals. the MAX7317 ignores all activity on sclk and din except when cs is low. note that the spi protocol expects dout to be high impedance when the MAX7317 is not being accessed; dout on the MAX7317 is never high impedance. go to www.maxim-ic.com/an1879 for ways to convert the MAX7317 to tri-state, if required. control and operation using the 4-wire interface controlling the MAX7317 requires sending a 16-bit word. the first byte, d15 through d8, is the command, and the second byte, d7 through d0, is the data byte (table 5). MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection _______________________________________________________________________________________ 5 figure 1. simplified schematic of i/o ports n read pulse input port register d q ff ck q input port register data d q ff ck q data from shift register write pulse output port register output port register data i/o pin gnd
MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection 6 _______________________________________________________________________________________ command address register d15 d14 d13 d12 d11 d10 d9 d8 code (hex) port p0 output level r/ w 0 0 0 0 0 0 0 0x00 port p1 output level r/ w 0 0 0 0 0 0 1 0x01 port p2 output level r/ w 0 0 0 0 0 1 0 0x02 port p3 output level r/ w 0 0 0 0 0 1 1 0x03 port p4 output level r/ w 0 0 0 0 1 0 0 0x04 port p5 output level r/ w 0 0 0 0 1 0 1 0x05 port p6 output level r/ w 0 0 0 0 1 1 0 0x06 port p7 output level r/ w 0 0 0 0 1 1 1 0x07 port p8 output level r/ w 0 0 0 1 0 0 0 0x08 port p9 output level r/ w 0 0 0 1 0 0 1 0x09 write ports p0 through p9 with same output level 0 read port p0 output level 1 0 0 0 1 0 1 0 0x0a write ports p0 through p3 with same output level 0 read port p0 output level 1 0 0 0 1 0 1 1 0x0b write ports p4 through p7 with same output level 0 read port p4 output level 1 0 0 0 1 1 0 0 0x0c write ports p8 or p9 with same output level 0 read port p8 output level 1 0 0 0 1 1 0 1 0x0d read ports p7 through p0 inputs 1 0 0 0 1 1 1 0 0x0e read ports p9 and p8 inputs 1 0 0 0 1 1 1 1 0x0f ram r/ w 0 0 1 0 0 1 1 0x13 no-op r/ w 0 1 0 0 0 0 0 0x20 factory reserved; do not write to this register r/ w 1 1 1 1 1 0 1 0x7d table 1. register address map register data register power-up condition address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 port p0 output level port 0 high impedance 0x00 1 1 11111 1 port p1 output level port 1 high impedance 0x01 1 1 11111 1 port p2 output level port 2 high impedance 0x02 1 1 11111 1 port p3 output level port 3 high impedance 0x03 1 1 11111 1 port p4 output level port 4 high impedance 0x04 1 1 11111 1 port p5 output level port 5 high impedance 0x05 1 1 11111 1 port p6 output level port 6 high impedance 0x06 1 1 11111 1 port p7 output level port 7 high impedance 0x07 1 1 11111 1 port p8 output level port 8 high impedance 0x08 1 1 11111 1 port p9 output level port 9 high impedance 0x09 1 1 11111 1 ram 0x00 0x13 0 0 00000 0 table 2. initial power-up register status
connecting multiple MAX7317s to the 4-wire bus multiple MAX7317s can be interfaced to a common spi bus by connecting din inputs together, sclk inputs together, and providing an individual cs per the MAX7317 device (figure 2). this connection works regardless of the configuration of dout/osc, but does not allow the MAX7317s to be read. MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection _______________________________________________________________________________________ 7 register data register r/ w address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 read input ports p7?0 1 0x0e port p7 port p6 port p5 port p4 port p3 port p2 port p1 port p0 read input ports p9, p8 1 0x0f 0 0 0 0 0 0 port p9 port p8 table 3. input ports register register data binary register r/ w address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 hex port p0 level msb output p0 level and pwm lsb port p0 is open-drain logic low 00000000 0x00 port p0 is open-drain logic high (high impedance without external pullup) or logic input 0x00 00000001 0x01 port p1 level 0x01 msb port p1 level lsb port p2 level 0x02 msb port p2 level lsb port p3 level 0x03 msb port p3 level lsb port p4 level ? 0x04 msb port p4 level lsb port p5 level 0x05 msb port p5 level lsb 0x00 or 0x01 port p6 level 0x06 msb port p6 level lsb port p7 level 0x07 msb port p7 level lsb port p8 level 0x08 msb port p8 level lsb port p9 level 0x09 msb port p9 level lsb writes ports p0 through p9 with same level 0 msb ports p0 through p9 level lsb reads port p0 level 1 0x0a msb port p0 level lsb writes ports p0 through p3 with same level 0 msb ports p0 through p3 level lsb reads port p0 level 1 0x0b msb port p0 level lsb writes ports p4 through p7 with same level 0 msb ports p4 through p7 level lsb reads port p4 level 1 0x0c msb port p4 level lsb write ports p8 and p9 with same level 0 msb ports p8, p9 level lsb read port p8 level 1 0x0d msb port p8 level lsb table 4. output registers format
MAX7317 alternatively, MAX7317s can be daisy-chained by con- necting the dout of one device to the din of the next, and driving sclk and cs lines in parallel (figure 3). this connection allows the MAX7317s to be read. data at din propagates through the internal shift registers and appears at dout 15.5 clock cycles later, clocked out on the falling edge of sclk. when sending com- mands to daisy-chained MAX7317s, all devices are accessed at the same time. an access requires (16 x n) clock cycles, where n is the number of MAX7317s con- nected together. the serial interface speed (maximum sclk) is limited to 10mhz when multiple devices are daisy-chained due to the dout propagation delay and din setup time. the MAX7317 is written to using the following sequence (figure 5): 1) take sclk low. 2) take cs low. this enables the internal 16-bit shift register. 3) clock 16 bits of data into din, d15 first to d0 last, observing the setup and hold times. bit d15 is low, indicating a write command. 4) take cs high (either while sclk is still high after clocking in the last data bit, or after taking sclk low). 5) take sclk low (if not already low). if fewer or greater than 16 bits are clocked into the MAX7317 between taking cs low and taking cs high again, the MAX7317 stores the last 16 bits received, including the previous transmission(s). the general case is when n bits (where n > 16) are transmitted to the MAX7317. the last bits comprising bits {n-15} to {n}, are retained, and are parallel loaded into the 16-bit latch as bits d15 to d0, respectively (figure 6). reading device registers any register data within the MAX7317 can be read by sending a logic high to bit d15. the sequence is: 1) take sclk low. 2) take cs low. this enables the internal 16-bit shift register. 3) clock 16 bits of data into din, d15 first to d0 last. d15 is high, indicating a read command and bits d14 through d8 contain the address of the register to read. bits d7 to d0 contain dummy data, which is discarded. 4) take cs high (either while sclk is still high after clocking in the last data bit, or after taking sclk low). positions d7 through d0 in the shift register are now loaded with the register data addressed by bits d15 through d8. 5) take sclk low (if not already low). 6) issue another read or write command, and examine the bit stream at dout; the second 8 bits are the contents of the register addressed by bits d14 through d8 in step 3. 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection 8 _______________________________________________________________________________________ d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/ w msb address lsb msb data lsb table 5. serial-data format figure 2. MAX7317 multiple cs connection din sclk cs3 din sclk cs2 din sclk mosi sclk cs1 cs3 cs2 cs1 MAX7317 MAX7317 MAX7317 c
MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection _______________________________________________________________________________________ 9 figure 3. MAX7317 daisy-chain connection sclk sclk din dout dout dout din din sclk mosi miso sclk cs cs cs cs MAX7317 MAX7317 MAX7317 c figure 5. 16-bit write transmission to the MAX7317 figure 4. timing diagram t css t cl t ch t csh t cp t csw cs sclk din dout t ds t dh t do d0 d15 d1 d14 d15 . d15 = 0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 = 0 cs sclk din dout
MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection 10 ______________________________________________________________________________________ applications information hot insertion the i/o ports p0?9 remain high impedance with up to 8v asserted on them when the MAX7317 is powered down (v+ = 0v). the MAX7317 can therefore be used in hot-swap applications. spi routing considerations the MAX7317? spi interface is guaranteed to operate at 26mbps on a 2.5v supply, and on a 3.3v supply typi- cally operates at 35mbps. this means that transmission line issues should be considered when the interface connections are longer than 100mm, particularly with higher supply voltages. avoid running long adjacent tracks for sclk, din, and cs without interleaving gnd traces; otherwise, the signals may cross-couple, giving false clock or chip-select transitions. ringing may man- ifest itself as communication issues, often intermittent, typically due to double clocking caused by ringing at the sclk input. fit a 1k ? to 10k ? parallel termination resistor to either gnd or v+ at the din, sclk, and cs inputs to damp ringing for moderately long interface runs. use line-impedance-matching terminations when making connections between boards. output-level translation the open-drain output architecture allows the ports to level translate the outputs to higher or lower voltages than the MAX7317 supply. an external pullup resistor can be used on any output to convert the high-imped- ance logic-high condition to a positive voltage level. the resistor can be connected to any voltage up to 7v. when using a pullup on a constant-current output, select the resistor value to sink no more than a few hun- dred ? in logic-low condition. this ensures that the current sink output saturates close to gnd. for inter- facing cmos inputs, a pullup resistor value of 220k ? is a good starting point. use a lower resistance to improve noise immunity in applications where power consumption is less critical, or where a faster rise time is needed for a given capacitive load. power-supply considerations the MAX7317 operates with a power-supply voltage of 2.25v to 3.6v. bypass the power supply to gnd with a 0.047? ceramic capacitor as close to the device as possible. for the qfn version, connect the underside exposed pad to gnd. chip information transistor count: 14,865 process: bicmos . n-15 n-31 n-30 n-29 n-28 n-27 n-26 n-25 n-24 n-23 n-22 n-21 n-20 n-19 n-18 n-17 n-16 bit 1 bit 2 n-14 n-13 n-12 n-11 n-10 n-9 n-8 n-7 n-6 n-5 n-4 n-3 n-2 n-1 n cs sclk din dout 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 sclk v+ din dout p9 p8 p7 p6 p5 top view MAX7317aee qsop cs p0 p3 p1 p2 p4 gnd pin configurations (continued) figure 6. transmission of more than 16 bits to the MAX7317
MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection ______________________________________________________________________________________ 11 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch
MAX7317 10-port spi-interfaced i/o expander with overvoltage and hot-insertion protection maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 12x16l qfn thin.eps 0.10 c 0.08 c 0.10 m c a b d d/2 e/2 e a1 a2 a e2 e2/2 l k e (nd - 1) x e (ne - 1) x e d2 d2/2 b l e l c l e c l l c l c e 1 2 21-0136 package outline 12, 16l, thin qfn, 3x3x0.8mm 1. dimensioning & tolerancing conform to asme y14.5m-1994. exposed pad variations 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220 revision c. notes: e 2 2 21-0136 package outline 12, 16l, thin qfn, 3x3x0.8mm down bonds allowed

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